Microchip Technology /ATSAME70Q21B /GMAC /NCFGR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as NCFGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPD)SPD 0 (FD)FD 0 (DNVLAN)DNVLAN 0 (JFRAME)JFRAME 0 (CAF)CAF 0 (NBC)NBC 0 (MTIHEN)MTIHEN 0 (UNIHEN)UNIHEN 0 (MAXFS)MAXFS 0 (RTY)RTY 0 (PEN)PEN 0RXBUFO 0 (LFERD)LFERD 0 (RFCS)RFCS 0 (MCK_8)CLK0DBW0 (DCPF)DCPF 0 (RXCOEN)RXCOEN 0 (EFRHD)EFRHD 0 (IRXFCS)IRXFCS 0 (IPGSEN)IPGSEN 0 (RXBP)RXBP 0 (IRXER)IRXER

CLK=MCK_8

Description

Network Configuration Register

Fields

SPD

Speed

FD

Full Duplex

DNVLAN

Discard Non-VLAN FRAMES

JFRAME

Jumbo Frame Size

CAF

Copy All Frames

NBC

No Broadcast

MTIHEN

Multicast Hash Enable

UNIHEN

Unicast Hash Enable

MAXFS

1536 Maximum Frame Size

RTY

Retry Test

PEN

Pause Enable

RXBUFO

Receive Buffer Offset

LFERD

Length Field Error Frame Discard

RFCS

Remove FCS

CLK

MDC CLock Division

0 (MCK_8): MCK divided by 8 (MCK up to 20 MHz)

1 (MCK_16): MCK divided by 16 (MCK up to 40 MHz)

2 (MCK_32): MCK divided by 32 (MCK up to 80 MHz)

3 (MCK_48): MCK divided by 48 (MCK up to 120 MHz)

4 (MCK_64): MCK divided by 64 (MCK up to 160 MHz)

5 (MCK_96): MCK divided by 96 (MCK up to 240 MHz)

DBW

Data Bus Width

DCPF

Disable Copy of Pause Frames

RXCOEN

Receive Checksum Offload Enable

EFRHD

Enable Frames Received in Half Duplex

IRXFCS

Ignore RX FCS

IPGSEN

IP Stretch Enable

RXBP

Receive Bad Preamble

IRXER

Ignore IPG GRXER

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